As the dimensions of semiconductor devices continue to shrink, the spacing between adjacent polysilicon gates decreases, the aspect ratio of the gaps between the gates increases, and filling of the gaps with a dielectric material becomes very challenging. As the gaps are actually formed between spacers of adjacent gates, the spacer profile is a key factor in a high-quality gap fill. Conventional spacers generally result in a substantially uniform gap width, leading to voids in the filled dielectric material. Voids in the interlayer dielectric (ILD) may cause shorts between drain contacts or between source contacts, thereby degrading device performance.
Achieving a void-free gap fill of dielectric material is particularly difficult between double-poly gates, for example having a height about 200 nanometers (nm), with tight spacing, e.g. having a minimum spacing of 108 nm, in a typical embedded non-volatile memory (eNVM) process flow. Adverting to FIG. 1A, each gate 101 includes a sidewall spacer 103 having an upper portion 105 and a lower portion 107. The lower portion may be characterized by sidewall angle 109, space 111, and height 113. As illustrated in FIG. 1B, when an ILD 115 is deposited over and between two adjacent gates 101, a void 117 is formed. Current process flows, such as deposition of a low temperature oxide (LTO) 201 to a thickness of 500 angstroms (Å) over gate 203 (as illustrated in FIG. 2A) followed by anisotropic top-down reactive ion etching (RIE), produce a sidewall spacer profile 205 (as illustrated in FIG. 2B) with a top corner rounded off and a large, substantially vertical, lower portion 207, for example having a height of 60 nm to 180 nm. The significant vertical portion is not favored by current ILD gap fill processes, such as a high aspect ratio process (HARP), causing formation of voids 117 during ILD gap fill.
A need therefore exists for methodology enabling formation of gate spacers having a tapered profile, and the resulting device.